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RDM General Implementation Discussion General Discussion and questions relating to implementing RDM in a product.

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Old February 23rd, 2012   #1
PeakPaul
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Default FRAMING ERROR Detection method

Hi All,

Does anyone use the UART "framing error" detection method for detecting the BREAK before MAB when using RDM?

This method works fine for DMX, but will it still hold water for RDM?

How are you guys controlling the timing of these events in your micros?

Regards

Paul.
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Old February 23rd, 2012   #2
ericthegeek
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A framing error isn't enough to reliably detect a break, especially in the presence of noise on the DMX line or during discovery.

Your best bet is to use a timer/counter to measure the amount of time that the line is held low. This allows you distinguish a framing error from a true break. If you see a framing error during an RDM packet, treat it like you would a checksum error and ignore the packet.
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Old February 24th, 2012   #3
PeakPaul
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Thanks Eric, I'll have to look into using an external interrupt on the UART pin, then switching the UART on when we have a valid break.
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Old March 2nd, 2012   #4
prwatE120
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It should be possible to use a timer in conjunction with the UART framing error detection, especially if you look at the data returned by the UART during the framing error.

I have many sucessfull DMX/RDM receiver designs that do not need to resort to using a second external irq.

I think want Eric meant is : "dont just assume that a Framing Error" is a break.

Peter
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Old March 2nd, 2012   #5
PeakPaul
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Thanks Peter for your reply, can you elaborate a bit more on the method of how to do this because once I've detected a FE, I will have lost an undetermined amount of time from the start of the break I assume?

Paul.
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Old March 3rd, 2012   #6
Nigel Worsley
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Quote:
Originally Posted by PeakPaul View Post
once I've detected a FE, I will have lost an undetermined amount of time from the start of the break
The exact amount of time will be dependent on the design of the UART, but should be fairly consistent. If using a typical 16x baud rate clock the variability would be +/- 0.125uS which is totally insignificant, the delay from the start of the break to the FE would typically be about 38uS - equivalent to the start bit, 8 data bits and the mid point of the stop bit. Some UARTS sample on 3 consecutive clocks in the middle of the bit and do a majority vote, which would add a bit to the delay but still less than 1uS.

Nigel Worsley
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Old March 8th, 2012   #7
prwatE120
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A bigger issue in timing accuracy may well be the latency of your interrupt handler. Nigel has already noted that the time between the start bit and the UART's determination of a FE will be failry consistent. Of course you also need to consider the "data" the UART acquired at the time of the FE. If it is not 0x00, it may well be a FE, but is most certainly not the beginning of a BREAK.

Peter
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