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Old March 3rd, 2012   #6
Nigel Worsley
Junior Member
Join Date: Jun 2006
Location: London
Posts: 13

Originally Posted by PeakPaul View Post
once I've detected a FE, I will have lost an undetermined amount of time from the start of the break
The exact amount of time will be dependent on the design of the UART, but should be fairly consistent. If using a typical 16x baud rate clock the variability would be +/- 0.125uS which is totally insignificant, the delay from the start of the break to the FE would typically be about 38uS - equivalent to the start bit, 8 data bits and the mid point of the stop bit. Some UARTS sample on 3 consecutive clocks in the middle of the bit and do a majority vote, which would add a bit to the delay but still less than 1uS.

Nigel Worsley
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