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Old May 26th, 2015   #7
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Join Date: Jan 2008
Posts: 102

Originally Posted by ericthegeek View Post
Unfortunately, no. The 2.8ms time includes time for transmission delay. Transparent Inline Devices (hubs, splitters, etc.) are allowed to delay the signal by up to 88us each way. The timing values given in the standard allow for up to 4 transparent inline devices, which gives a round-trip delay of 704us. See E1.20-2010 Section 4.2.2.

The other problem you're going to run into is that if you wait until the end of the response time to get the DMA interrupt and start processing the packet, you'll have no time left to process the request and send the response before the controller gives up and assumes the response was lost.

Eric, I know.

The responder has no chance of processing the packet due to OS lag. that is why we are responding with ACK_TIMER as already discussed in another thread here.

I am not sure how we can proceed to make this work.
I guess the original spec designers never factored in that some systems need to use interslot timeouot to determine packet length. It is really a very common way to do it and the processors even cater for it with register settings and a special interrupt.

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