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Old March 30th, 2007   #3
Dan Scheurell
Junior Member
Join Date: Mar 2007
Location: Middleton, Wisconsin, USA
Posts: 4

Thank you, Peter, this is just the kind of answer I was looking for.

We have a separate timer, with separate interrupt, that is used to handle break and MAB timing. (Separate from the UART, that is.) So the interslot time is not an issue, that's handled by the UART itself. Total packet time is also compliant. The interrupt priorities are mostly fixed (MPC852 running Vxworks,) unless I modify the OS code. The timer interrupt is being preempted by other DMX ports and the system clock. This is, indeed, an intermittent problem that occurs too often when busy and interrupts align just so.

I'll bring the MAB time into spec range somehow, probably modifying the OS code to give higher priority to these particular timer interrupts, as you suggest.

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