Timing contraints driver switch from controller to responder
Hi there,
New on this forum, and to rdm for that matter. I hope someone can help me to clear up some timing details that I can not seem to find in the E1.20 specs. I am currently working on implementation of a rdm responder in a LPC11xx MCU. The issue I am facing is that in the situation of a controller doing a request to a responder, with an expected response, I am not entirely clear as to what the timing constraints are w.r.t. the bus (drive) switch from controller to responder. What I understand from the specs is that after the last stop bit is sent by the controller, the controller keeps driving the bus with MBB for a maximum of 88usec. After this time (or before), the controller stops driving the bus. I do not think the responder can detect the bus not being driven anylonger, as the biasing circuitry will pull the bus high if undriven (true?). Does this mean that the responder will always have to wait the full 88usec before it can initiate a break? If the responder starts its break earlier, we can not garantee the minimum break time (176usec). Can anyone elaborate? Any help would be most welcome! Thanks. Meindert Koelman |
Quote:
The biasing circuitry will pull the bus high when it is un-driven, but this can take a while due to capacitance on the wire. That's why RDM devices are required to drive the bus high before they disable their line drivers. This way the bias circuit only has to maintain the bus state, not change it. Quote:
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Dear Eric,
Thank you for your swift reply. It is clear now. Kind regards, Meindert |
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