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Old April 29th, 2010   #8
ericthegeek
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Join Date: Aug 2008
Posts: 355
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> Most UARTs sample each bit 16 times. If the bit is
> shortened by 7.5%, the UART would see 15 low
> samples and one high sample, well within tolerance.

Most *decent* UARTs use 16x sampling. Many of the 8051-derived UARTs are not nearly so sophisticated and only sample once per bit.

In the real world, you can probably drop a hundred nanoseconds or so off of the start bit and be OK. If your switching logic drops this much, you may not be able to use slew-rate limited drivers since they can introduce further asymmetry into the 485 line. I'd also suggest using a crystal oscillator rather than an internal osc. or RC since these can further cut into your timing margins.

Obviously it's nice to hew as close to the standard as you can, but sometimes you have to make reasonable compromises based on real-world behavior.
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